4° Off-Axis Cutting: The Hidden Angle That Decides Your SiC Epitaxial Layer Quality

Pick up a SiC (silicon carbide) wafer and measure its cut angle, and you’ll almost certainly find a strange number: not 0°, but 4°. That’s not a machining error — it’s deliberate. And this seemingly minor 4° is what largely decides whether the epitaxial layer grown on top turns out well, and ultimately how high your device yield can go.

Let’s walk through where this angle comes from, why it has to be roughly this value, and what problem it’s actually solving.

First, a Quirk of SiC

The biggest difference between silicon carbide and silicon is that SiC doesn’t have just one crystal structure. Even with Si and C arranged in the same 1:1 ratio, changing the stacking sequence produces hundreds of different “polytypes.” The one used most in commercial devices is 4H-SiC, whose atomic layers stack in an ABCB sequence, repeating every four layers.

That ABCB sequence looks simple, but it’s finicky to grow correctly. If you try to grow an epitaxial layer directly on a (0001) plane — a perfectly flat surface — the newly arriving atoms have a hard time stacking precisely in the right ABCB rhythm. It’s easy for the wrong stacking order to sneak in, producing parasitic 3C-SiC inclusions or stacking faults. Once these defects get mixed into the epitaxial layer, leakage current and breakdown voltage both suffer — which is basically a disaster for power devices.

Put simply, the root of the problem is that on a perfectly flat crystal plane, atoms have no “handhold” telling them where to land or in what order to stack.

Off-Axis Cutting: Giving Atoms a Staircase

The fix is to cut the wafer at a tilt away from the (0001) plane, toward the <11-20> direction. The mainstream choice in the industry today is 4°.

After cutting at this angle, the wafer surface is no longer one atomically flat plane. Instead it becomes a series of countless atomic-scale steps — what’s known as a “terrace-step” structure. Each terrace is only a few nanometers wide, bordered by a step that’s a single atomic layer high.

This solves most of the problem at once. During epitaxial growth, incoming Si and C atoms no longer have to “guess” how to arrange themselves — they preferentially attach to the edges of the steps and continue growing along the existing ABCB stacking order. This process is called step-flow growth. It’s like laying down a ready-made staircase for the atoms: they just walk up it, with little chance of veering off into the wrong polytype.

Why 4°, Not 8°, and Not 1°

In the early days of SiC epitaxy, the industry used an 8° off-axis angle, and it worked well — step-flow growth was very stable. But the downside was just as direct: the larger the cut angle, the fewer wafers you can slice out of a single boule, which drives up wafer cost. Cutting at 8° yields roughly half as many usable wafers per boule compared to 4°. For an industry trying to scale SiC toward mass commercialization, that cost gap is a serious problem.

So the industry gradually pushed the angle down, and 4° became the current sweet spot — small enough to save substantial wafer cost, but not so small that it breaks step-flow growth.

This is really a continuous trade-off, where the angle and the terrace width are roughly inversely related: the smaller the angle, the wider the terrace, and the farther an atom has to travel from where it lands to where it finds a step edge. If that distance is too long, the atom may nucleate on its own in the middle of the terrace before ever reaching a step, forming a new island and disrupting the otherwise clean step flow. When the angle is too small (below roughly 2°-3°), this problem becomes noticeably worse — surface roughness of the epitaxial layer increases, and you can even see macroscopic step bunching, producing visible streak-like defects on the surface.

On the other hand, a larger angle makes step-flow growth more robust, but it trades cost for quality in a way that isn’t worth it. 4° is essentially the balance point between “enough atomic migration distance” and “high enough wafer yield per boule.”

A More Hidden Issue: Dislocations

SiC substrates naturally contain a type of defect called basal plane dislocations (BPDs), which lie within the crystal’s basal plane. If they extend unchanged into the epitaxial layer, they can gradually expand into stacking faults during device operation, causing forward voltage drift — a long-standing reliability headache for SiC bipolar devices and even some MOSFETs.

The good news is that off-axis cutting incidentally helps with this too. Because the cut angle tilts the basal plane relative to the wafer surface, BPDs that would otherwise lie flat in the basal plane have a good chance of being “bent” as epitaxial growth crosses the interface, converting into far less harmful threading edge dislocations (TEDs). TEDs run vertically through the epitaxial layer instead of propagating laterally, so they don’t cause the same problem.

This conversion efficiency is also directly tied to the off-axis angle. At the right angle, the BPD-to-TED conversion rate can be quite high — which is another reason 4° hasn’t been pushed any lower. Too small an angle, and the conversion rate drops along with it.

Cutting Precision: A Simple Number, a Sub-Degree Job

4° sounds like a simple number, but in practice, manufacturing has to guarantee that the off-axis angle stays uniform across every point on the wafer. The boule itself has slight crystallographic deviations as it grows, and any imprecision in the cutting equipment’s orientation or in how the wafer is clamped can cause the actual off-axis angle to vary from one location to another on the same wafer.

Angle non-uniformity shows up directly as non-uniformity in the epitaxial layer — the terrace width differs between the wafer’s edge and center, growth rate and doping concentration drift accordingly, and in the end, chip yield varies significantly across different positions on the same wafer. This is why substrate suppliers keep the tolerance on off-axis angle very tight, typically within ±0.1° or even less.

Closing Thoughts

At first glance, 4° looks like just a geometric parameter for cutting a wafer. But behind it lies a shared trade-off among crystal structure, growth kinetics, defect engineering, and industrial cost. There’s a saying in SiC epitaxy that gets right to the point: the substrate sets the floor, the epitaxy sets the ceiling — and the off-axis angle is exactly the line connecting the two.

Next time you see “4° off-axis” on a SiC wafer spec sheet, you’ll know just how much process know-how is packed into those three words.