N-Type or Semi-Insulating: What Really Sets a 6-Inch SiC Substrate Apart

Silicon carbide (SiC) substrates are the “foundation” of power devices and RF devices — the flatness, purity, and defect density of that foundation directly determine what kind of “building” can be constructed on top of it.

I. Two Product Lines, Two Application Directions

SiC substrates fall into two major categories based on conductivity, corresponding to entirely different downstream applications:

● Conductive (N-Type) substrates: resistivity is engineered very low (Semicera’s version reaches 0.015–0.030 Ω·cm), primarily used to fabricate vertical-structure power devices such as SiC MOSFETs and SBDs (Schottky barrier diodes). Since current must flow vertically through the substrate, the substrate itself must be highly conductive.

● High-purity semi-insulating (HPSI) substrates: resistivity is engineered extremely high (this article’s version starts at a minimum of 1E5 Ω·cm, with higher grades reaching ≥1E10 Ω·cm), primarily used for GaN-on-SiC RF devices — in scenarios such as 5G base stations, radar, and satellite communications, where the substrate must be non-conductive to minimize parasitic loss of RF signals.

One low, one high — these two resistivity ranges may look like a difference in a single parameter, but behind them lie two completely different crystal growth and doping control processes.

II. Conductive Substrates: Graded by Downstream Device

Semicera’s 6-inch conductive substrates are divided into four grades — MOS1, MOS2, SBD, and Dummy. The higher the grade, the lower the process tolerance of the corresponding device, and therefore the tighter the specification. A few key parameters illustrate the differences:

Why are MOS-grade requirements the strictest? A SiC MOSFET’s gate oxide layer is grown directly on top of the substrate’s epitaxial layer; any micropipe or dislocation defect can trigger localized electric field concentration at the gate oxide interface, leading to reduced breakdown voltage or even leakage failure. Basal plane dislocations (BPDs) in particular — if not effectively converted during epitaxial growth — can expand into stacking faults during long-term device operation, causing forward voltage degradation in bipolar devices (this is also one of the root causes of the “bipolar degradation” issue that has long concerned the SiC bipolar device industry).

SBD grade is comparatively relaxed, because Schottky barrier diodes are majority-carrier devices and are less sensitive to bulk dislocations than the channel region of a MOSFET, so defect density limits can be loosened somewhat, reducing cost.

Dummy grade (companion / process-qualification wafers) does not involve final device performance and is mainly used for production-line equipment debugging and process parameter validation, so naturally it carries the loosest specification of the four tiers — but note that “lose” is relative: a micropipe density ≤1 cm⁻² and TTV ≤10μm is still not a low bar within the substrate industry as a whole.

III. Semi-Insulating Substrates: Resistivity Is the Core Threshold

HPSI substrates follow a slightly different grading logic — the core factor is how high the resistivity can be pushed:

A common way to achieve high resistivity in semi-insulating substrates is to introduce vanadium (V) doping during crystal growth, or to precisely control intrinsic point defects (such as carbon vacancies) to achieve deep-level compensation — trapping carriers in deep-level traps and pushing bulk resistivity up into the 10⁸–10¹⁰ Ω·cm range. This is also why the process window for growing HPSI substrates is narrower than for conductive substrates: resistivity is extremely sensitive to impurity concentration and the growth temperature field, and even a slight deviation can push an entire wafer’s resistivity out of the target range.

Worth noting is the (0004) plane XRD rocking curve full width at half maximum (FWHM) — this parameter reflects the microscopic strain and dislocation density distribution inside the crystal; the smaller the value, the more regular the lattice arrangement. This metric is not typically treated as a core indicator on conductive-substrate spec sheets, but it is listed separately for HPSI substrates, because RF devices require a level of crystal integrity that is closer to an “optical-grade” standard.

IV. A Few Easily Overlooked but Critical Parameters

Beyond resistivity and micropipe density — the “headline parameters” — spec sheets contain several other parameters that buyers often overlook, yet which have a major impact on yield:

Surface Roughness (Ra): Both spec sheets require Ra < 0.2nm on the Si-face after CMP polishing (measured by AFM over a 10μm×10μm area). This value directly determines the starting interface quality for epitaxial growth — every incremental increase in roughness noticeably raises the probability of introducing step-bunching defects into the epitaxial layer.

BOW / WARP: These two parameters are easily mistaken for the same thing. BOW describes the overall bending direction and magnitude of the substrate center relative to its edge, while WARP is the total deviation of the substrate surface from an ideal flat plane. Both affect depth-of-focus control in subsequent lithography steps — particularly on power-device production lines using high-precision lithography, where out-of-spec warpage can directly cause edge exposure to go out of focus.

Particle Contamination (>0.3μm) and Surface Metal Contamination: The spec sheets limit total surface contamination from metal elements — including K, Ca, Ti, V, Cr, Mn, Fe, Ni, Cu, Zn, Al, Na, and Hg — to below 5E10 atoms/cm². Once these metallic impurities diffuse into the active region during high-temperature steps of epitaxy or device processing, they form deep-level recombination centers that directly reduce minority-carrier lifetime — an effect that is especially pronounced for bipolar and high-voltage devices.

V. Selection Recommendations

For engineers currently evaluating 6-inch SiC substrate suppliers, here are a few practical angles to consider:

● Match the grade to the device type first: if you’re making MOSFETs, don’t cut costs by choosing SBD-grade substrates — dislocation density differs by an order of magnitude, and the yield risk is completely disproportionate to the savings; conversely, if you’re making SBDs, there’s no need to pay the premium for MOS1 grade.

● For HPSI substrates, focus on verifying resistivity uniformity, not just the average value — excessive resistivity variation within a single batch will cause the RF performance of GaN epitaxial wafers from that same batch to scatter.

● Don’t look only at micropipe density — dislocation data matters too: micropipes are the most visually obvious “fatal defect,” but basal plane dislocation and threading screw dislocation density can just as easily surface problems during long-term device reliability testing, especially in scenarios requiring long-term qualification (such as automotive-grade devices).

Conclusion

On the surface, a 6-inch SiC substrate spec sheet is just a dense block of numbers, but every single entry corresponds to a specific failure mechanism and process consideration. As domestic SiC substrate manufacturers steadily close the gap with international first-tier players on micropipe density and dislocation control, “are the parameters good enough” is no longer the only question — “can batch-to-batch consistency be reliably reproduced” is emerging as the new metric that downstream device manufacturers care about most.