Compound Semiconductor Substrate Wafers: From Crystal Growth to Photonic Integration

1. Crystal Growth: The Fundamental Difference Between VGF and LEC

The growth of gallium arsenide (GaAs), indium phosphide (InP) and other III-V single crystals is dominated industrially by two technology routes: Liquid Encapsulated Czochralski (LEC) and Vertical Gradient Freeze (VGF). Both methods pull or solidify a single-crystal boule from a melt, but their thermal-field designs differ fundamentally, and that difference directly determines the resulting wafer’s defect density and geometric characteristics.

In LEC, a layer of B₂O₃ (boric oxide) encapsulant covers the melt surface to prevent high-vapor-pressure constituents (such as phosphorus in InP) from escaping at high temperature. A seed crystal is inserted from the top and rotated as it is pulled to form the boule. This process has a longer industrial history and a more mature equipment base, but because the axial and radial temperature gradients during growth are relatively large, thermal stress is higher, and dislocations, slip, and long-range strain are more easily introduced into the crystal.

VGF instead places the seed at the bottom of the crucible (typically a PBN, pyrolytic boron nitride, crucible) and directionally solidifies the melt from bottom to top by slowly shifting the temperature field, with a much lower overall gradient than LEC. Early work from Bell Labs reported that, under comparable conditions, GaAs, InP and GaP crystals grown by VGF showed dislocation densities roughly two orders of magnitude lower than LEC-grown material. Later Raman-stress characterization work reached a related conclusion: VGF-grown InP and InAs wafers achieve better overall flatness, but their residual-stress distribution differs from that of LEC wafers, and the two routes tend toward different defect types — LEC is more prone to long-range strain and slip, while VGF is relatively more prone to twinning.

This is why, in practice, choosing a crystal-growth route is never simply a matter of “which technology is more advanced” — it is an engineering trade-off matched to how tolerant a given device is of substrate defects:

2. Reading a Wafer Spec Sheet: What the Key Parameters Actually Mean

Whether for semi-insulating GaAs, Fe-doped InP, or Te-doped n-type GaSb/InSb, a complete wafer spec sheet or product certificate typically covers a consistent set of parameter categories. These are not isolated numbers — they are interrelated engineering constraints that together determine downstream device yield:

For example, semi-insulating GaAs substrates for high-frequency microwave devices typically need resistivity above roughly 10⁷ Ω·cm and etch pit density kept to a few thousand cm⁻² or below to meet substrate-isolation requirements. Fe-doped InP substrates used for laser/detector epitaxy, on the other hand, are more sensitive to doping uniformity — uneven iron distribution causes dislocations to cluster in locally iron-depleted regions, a long-standing engineering challenge common to both VGF and LEC growth.

3. From InP Substrates to Photonic Integrated Circuits: The Material Basis of Heterogeneous Integration

Over the past few years, demand from AI data centers for 800G and even 1.6T/3.2T optical modules has made InP-on-silicon heterogeneous integration one of the most closely watched routes in silicon photonics. Platforms such as Tower Semiconductor’s PH18DA process — and the PASIC design capability that OpenLight offers on top of it — are built around bonding or epitaxially transferring active InP-based components (lasers, amplifiers, modulators) at the wafer level onto a mature, low-cost silicon photonics platform, combining silicon photonics’ manufacturing scale with InP’s direct-gain optical properties on a single chip.

This route places stricter demands on the upstream InP substrate. On one hand, as the starting substrate for active-layer epitaxy, its dislocation density directly determines laser reliability and threshold current. On the other hand, the bonding/transfer process imposes near-strict uniformity requirements on substrate flatness (TTV, warp) and surface condition — batch-to-batch parameter variation translates directly into wafer-level yield variation. This is also why the industry increasingly relies on epi-ready certification and per-wafer test reports (such as min/max ranges for carrier concentration and mobility) for InP substrates.

4. Narrow-Gap Materials: GaSb and InSb for Infrared Detection

Unlike GaAs and InP, which mainly serve communications and photonic applications, gallium antimonide (GaSb) and indium antimonide (InSb) are narrow-bandgap compound semiconductors, with room-temperature bandgaps of roughly 0.7 eV and 0.17 eV respectively. This makes them naturally suited to mid-infrared detection (GaSb-based devices typically covering 1.7–4.3 µm) and mid- to long-wave infrared detection (InSb-based detectors covering roughly 3–5 µm and beyond).

These substrates are typically grown by LEC and doped with tellurium to form n-type conductive material, with process control focused on carrier-concentration uniformity and dislocation density (EPD), since infrared detectors are highly sensitive to dark current and response uniformity, both of which are directly tied to crystal integrity. Compared with InP, GaSb/InSb applications are more vertically specific and lower in volume than communications-grade materials, but the requirement for per-wafer consistency is equally strict — one reason supplier concentration in these narrow-gap substrate markets has historically remained high.

5. Summary

From the choice between LEC and VGF growth, to the string of spec parameters — EPD, TTV, mobility and more — to the near-exacting substrate-consistency demands of InP-on-silicon heterogeneous integration, the technical barrier in compound semiconductor wafers ultimately comes down to one question, expressed differently across material systems: how to translate the physical characteristics established during crystal growth into engineering parameters that downstream device makers can rely on, wafer after wafer. Understanding the physics behind these parameters is also the starting point for judging whether a wafer spec sheet or product certificate is genuinely usable.