SOI Wafer Silicon On Insulator

Semicera’s SOI Wafer (Silicon On Insulator) provides exceptional electrical isolation and performance for advanced semiconductor applications. Engineered for superior thermal and electrical efficiency, these wafers are ideal for high-performance integrated circuits. Choose Semicera for quality and reliability in SOI wafer technology.

Semicera’s SOI Wafer (Silicon On Insulator) is designed to deliver superior electrical isolation and thermal performance. This innovative wafer structure, featuring a silicon layer on an insulating layer, ensures enhanced device performance and reduced power consumption, making it ideal for a variety of high-tech applications.

Our SOI wafers offer exceptional benefits for integrated circuits by minimizing parasitic capacitance and improving device speed and efficiency. This is crucial for modern electronics, where high performance and energy efficiency are essential for both consumer and industrial applications.

Semicera employs advanced manufacturing techniques to produce SOI wafers with consistent quality and reliability. These wafers provide excellent thermal insulation, making them suitable for use in environments where heat dissipation is a concern, such as in high-density electronic devices and power management systems.

The use of SOI wafers in semiconductor fabrication allows for the development of smaller, faster, and more reliable chips. Semicera’s commitment to precision engineering ensures that our SOI wafers meet the high standards required for cutting-edge technologies in fields like telecommunications, automotive, and consumer electronics.

Choosing Semicera’s SOI Wafer means investing in a product that supports the advancement of electronic and microelectronic technologies. Our wafers are designed to provide enhanced performance and durability, contributing to the success of your high-tech projects and ensuring that you stay at the forefront of innovation.

Articles

Production

Recherche

Factice

Paramètres de cristal

Polytype

4H

Erreur d'orientation de la surface

4±0.15°

Paramètres électriques

Dopant

azote de type N

Résistivité

0,015-0.025ohm · cm

Paramètres mécaniques

Diamètre

150,0 ± 0,2 mm

Épaisseur

350 ± 25 µm

Orientation plate primaire

[1-100]±5°

Longueur plate primaire

47,5 ± 1,5 mm

Plat secondaire

Aucun

TTV

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5 mm * 5 mm)

≤5 μm (5 mm * 5 mm)

≤10 μm (5 mm * 5 mm)

Arc

-15 μm ~ 15μm

-35 μm ~ 35 μm

-45 μm ~ 45 μm

Chaîne

≤35 µm

≤45 µm

≤55 µm

Rugosité avant (si-face) (AFM)

Ra≤0,2 nm (5 μm * 5 μm)

Structure

Densité de micro-

<1 ea / cm2

<10 ea / cm2

<15 ea / cm2

Impuretés métalliques

≤5E10atoms/cm2

N / A

BPB

≤1500 ea / cm2

≤3000 ea / cm2

N / A

TSD

≤500 ea / cm2

≤1000 ea / cm2

N / A

Qualité avant

Devant

Si

Finition de surface

CMP SI-FACE

Particules

≤60ea / plaquette (taille 0,3 μm)

N / A

Rayures

≤5EA / MM. Longueur cumulative ≤ diamètre

Longueur cumulatif ≤2 * diamètre

N / A

PELLE / PEPES ORANGE / TAPPES / COMMENTS / CRESCHES / CONTAMINATION

Aucun

N / A

Coups de bord / retraits / fracture / plaques hexagonales

Aucun

Zones de polytype

Aucun

Zone cumulative≤20%

Zone cumulative ≤ 30%

Marquage laser avant

Aucun

Qualité du dos

Finition arrière

CMP C-FACE

Rayures

≤5ea / mm, longueur cumulative≤2 * diamètre

N / A

Défauts arrière (puces de bord / retraits)

Aucun

Rugosité du dos

Ra≤0,2 nm (5 μm * 5 μm)

Marquage laser arrière

1 mm (du bord supérieur)

Bord

Bord

Chanfreiner

Conditionnement

Conditionnement

Préparé en épi avec un emballage sous vide

Emballage de cassette multi-wafer

*Remarques: «NA» signifie qu'aucun élément de demande non mentionné ne peut se référer au semi-std.

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