Semicera 3C-SiC Wafer Substrates offer superior thermal conductivity and high electrical breakdown voltage, ideal for power electronic and high-frequency devices. These substrates are precision-engineered for optimal performance in harsh environments, ensuring reliability and efficiency. Choose Semicera for innovative and advanced solutions.
Semicera 3C-SiC Wafer Substrates are engineered to provide a robust platform for next-generation power electronics and high-frequency devices. With superior thermal properties and electrical characteristics, these substrates are designed to meet the demanding requirements of modern technology.
The 3C-SiC (Cubic Silicon Carbide) structure of Semicera Wafer Substrates offers unique advantages, including higher thermal conductivity and a lower thermal expansion coefficient compared to other semiconductor materials. This makes them an excellent choice for devices operating under extreme temperatures and high-power conditions.
With a high electrical breakdown voltage and superior chemical stability, Semicera 3C-SiC Wafer Substrates ensure long-lasting performance and reliability. These properties are critical for applications such as high-frequency radar, solid-state lighting, and power inverters, where efficiency and durability are paramount.
Semicera’s commitment to quality is reflected in the meticulous manufacturing process of their 3C-SiC Wafer Substrates, ensuring uniformity and consistency across every batch. This precision contributes to the overall performance and longevity of the electronic devices built upon them.
By choosing Semicera 3C-SiC Wafer Substrates, manufacturers gain access to a cutting-edge material that enables the development of smaller, faster, and more efficient electronic components. Semicera continues to support technological innovation by providing reliable solutions that meet the evolving demands of the semiconductor industry.
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Elementi |
Produzione |
Ricerca |
Manichino |
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Parametri cristallini |
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Politipo |
4H |
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Errore di orientamento della superficie |
4±0.15° |
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Parametri elettrici |
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Drogante |
azoto di tipo n |
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Resistività |
0,015-0,025ohm · cm |
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Parametri meccanici |
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Diametro |
150,0 ± 0,2 mm |
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Spessore |
350 ± 25 µm |
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Orientamento piatto primario |
[1-100]±5° |
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Lunghezza piatta primaria |
47,5 ± 1,5 mm |
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Piatto secondario |
Nessuno |
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TTV |
≤5 µm |
≤10 µm |
≤15 µm |
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LTV |
≤3 μm (5mm*5mm) |
≤5 μm (5 mm*5 mm) |
≤10 μm (5 mm*5 mm) |
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Arco |
-15μm ~ 15μm |
-35μm ~ 35 μm |
-45μm ~ 45μm |
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Ordito |
≤35 µm |
≤45 µm |
≤55 µm |
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Front (Si-Face) Rughess (AFM) |
RA≤0,2 nm (5μm*5μm) |
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Struttura |
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Densità di micrivipe |
<1 ea/cm2 |
<10 ea/cm2 |
<15 ea/cm2 |
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Impurità dei metalli |
≤5E10atoms/cm2 |
N / A |
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BPD |
≤1500 ea/cm2 |
≤3000 ea/cm2 |
N / A |
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TSD |
≤500 ea/cm2 |
≤1000 ea/cm2 |
N / A |
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Qualità anteriore |
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Davanti |
Si |
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Finitura superficiale |
Si-Face CMP |
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Particelle |
≤60ea/wafer (dimensione≥0,3μm) |
N / A |
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Graffi |
≤5ea/mm. Lunghezza cumulativa ≤Diameter |
Diametro cumulativo della lunghezza ≤2* |
N / A |
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Buccia/pozzi/macchie/striature/crepe/contaminazione |
Nessuno |
N / A |
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Bordo chips/riendi/frattura/piastre esadecimale |
Nessuno |
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Aree politepi |
Nessuno |
Area cumulativa≤20% |
Area cumulativa≤30% |
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Marcatura laser anteriore |
Nessuno |
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Qualità alla schiena |
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Finitura posteriore |
C-FACE CMP |
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Graffi |
≤5ea/mm, lunghezza cumulativa≤2*diametro |
N / A |
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Difetti posteriori (bordo chip/rientri) |
Nessuno |
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Rugosità posteriore |
RA≤0,2 nm (5μm*5μm) |
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Marcatura laser sul retro |
1 mm (dal bordo superiore) |
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Bordo |
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Bordo |
Smussare |
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Confezione |
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Confezione |
Prepasto EPI con imballaggio a vuoto Packaging a cassette multi-wafer |
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*Note : “NA” significa che nessuna richiesta di richiesta non menzionata può fare riferimento a semi-std. |
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