4 Inch High Purity Semi-Insulating HPSI SiC Double-side Polished Wafer Substrate

Semicera’s 4 Inch High Purity Semi-Insulating (HPSI) SiC Double-side Polished Wafer Substrates are precision-engineered for superior electronic performance. These wafers provide excellent thermal conductivity and electrical insulation, ideal for advanced semiconductor applications. Trust Semicera for unparalleled quality and innovation in wafer technology.

Semicera’s 4 Inch High Purity Semi-Insulating (HPSI) SiC Double-side Polished Wafer Substrates are crafted to meet the exacting demands of the semiconductor industry. These substrates are designed with exceptional flatness and purity, offering an optimal platform for cutting-edge electronic devices.

These HPSI SiC wafers are distinguished by their superior thermal conductivity and electrical insulation properties, making them an excellent choice for high-frequency and high-power applications. The double-side polishing process ensures minimal surface roughness, which is crucial for enhancing device performance and longevity.

The high purity of Semicera’s SiC wafers minimizes defects and impurities, leading to higher yield rates and device reliability. These substrates are suitable for a wide range of applications, including microwave devices, power electronics, and LED technologies, where precision and durability are essential.

With a focus on innovation and quality, Semicera utilizes advanced manufacturing techniques to produce wafers that meet the stringent requirements of modern electronics. The double-sided polishing not only improves the mechanical strength but also facilitates better integration with other semiconductor materials.

By choosing Semicera’s 4 Inch High Purity Semi-Insulating HPSI SiC Double-side Polished Wafer Substrates, manufacturers can leverage the benefits of enhanced thermal management and electrical insulation, paving the way for the development of more efficient and powerful electronic devices. Semicera continues to lead the industry with its commitment to quality and technological advancement.

Elementi

Produzione

Ricerca

Manichino

Parametri cristallini

Politipo

4H

Errore di orientamento della superficie

4±0.15°

Parametri elettrici

Drogante

azoto di tipo n

Resistività

0,015-0,025ohm · cm

Parametri meccanici

Diametro

150,0 ± 0,2 mm

Spessore

350 ± 25 µm

Orientamento piatto primario

[1-100]±5°

Lunghezza piatta primaria

47,5 ± 1,5 mm

Piatto secondario

Nessuno

TTV

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5mm*5mm)

≤5 μm (5 mm*5 mm)

≤10 μm (5 mm*5 mm)

Arco

-15μm ~ 15μm

-35μm ~ 35 μm

-45μm ~ 45μm

Ordito

≤35 µm

≤45 µm

≤55 µm

Front (Si-Face) Rughess (AFM)

RA≤0,2 nm (5μm*5μm)

Struttura

Densità di micrivipe

<1 ea/cm2

<10 ea/cm2

<15 ea/cm2

Impurità dei metalli

≤5E10atoms/cm2

N / A

BPD

≤1500 ea/cm2

≤3000 ea/cm2

N / A

TSD

≤500 ea/cm2

≤1000 ea/cm2

N / A

Qualità anteriore

Davanti

Si

Finitura superficiale

Si-Face CMP

Particelle

≤60ea/wafer (dimensione≥0,3μm)

N / A

Graffi

≤5ea/mm. Lunghezza cumulativa ≤Diameter

Diametro cumulativo della lunghezza ≤2*

N / A

Buccia/pozzi/macchie/striature/crepe/contaminazione

Nessuno

N / A

Bordo chips/riendi/frattura/piastre esadecimale

Nessuno

Aree politepi

Nessuno

Area cumulativa≤20%

Area cumulativa≤30%

Marcatura laser anteriore

Nessuno

Qualità alla schiena

Finitura posteriore

C-FACE CMP

Graffi

≤5ea/mm, lunghezza cumulativa≤2*diametro

N / A

Difetti posteriori (bordo chip/rientri)

Nessuno

Rugosità posteriore

RA≤0,2 nm (5μm*5μm)

Marcatura laser sul retro

1 mm (dal bordo superiore)

Bordo

Bordo

Smussare

Confezione

Confezione

Prepasto EPI con imballaggio a vuoto

Packaging a cassette multi-wafer

*Note : “NA” significa che nessuna richiesta di richiesta non menzionata può fare riferimento a semi-std.

tech_1_2_size

Sic Wafer

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