SOI Wafer Silicon On Insulator

Semicera’s SOI Wafer (Silicon On Insulator) provides exceptional electrical isolation and performance for advanced semiconductor applications. Engineered for superior thermal and electrical efficiency, these wafers are ideal for high-performance integrated circuits. Choose Semicera for quality and reliability in SOI wafer technology.

Semicera’s SOI Wafer (Silicon On Insulator) is designed to deliver superior electrical isolation and thermal performance. This innovative wafer structure, featuring a silicon layer on an insulating layer, ensures enhanced device performance and reduced power consumption, making it ideal for a variety of high-tech applications.

Our SOI wafers offer exceptional benefits for integrated circuits by minimizing parasitic capacitance and improving device speed and efficiency. This is crucial for modern electronics, where high performance and energy efficiency are essential for both consumer and industrial applications.

Semicera employs advanced manufacturing techniques to produce SOI wafers with consistent quality and reliability. These wafers provide excellent thermal insulation, making them suitable for use in environments where heat dissipation is a concern, such as in high-density electronic devices and power management systems.

The use of SOI wafers in semiconductor fabrication allows for the development of smaller, faster, and more reliable chips. Semicera’s commitment to precision engineering ensures that our SOI wafers meet the high standards required for cutting-edge technologies in fields like telecommunications, automotive, and consumer electronics.

Choosing Semicera’s SOI Wafer means investing in a product that supports the advancement of electronic and microelectronic technologies. Our wafers are designed to provide enhanced performance and durability, contributing to the success of your high-tech projects and ensuring that you stay at the forefront of innovation.

항목

생산

연구

더미

결정 매개 변수

폴리 타입

4H

표면 방향 오류

4±0.15°

전기 매개 변수

도펀트

N- 타입 질소

저항

0.015-0.025ohm · cm

기계적 매개 변수

지름

150.0 ± 0.2mm

두께

350 ± 25 µm

1 차 평평한 방향

[1-100]±5°

1 차 평평한 길이

47.5 ± 1.5mm

보조 아파트

없음

TTV

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5mm*5mm)

≤5 μm (5mm*5mm)

≤10 μm (5mm*5mm)

절하다

-15μm ~ 15μm

-35μm ~ 35μm

-45μm ~ 45μm

경사

≤35 µm

≤45 µm

≤55 µm

전면 (si-face) 거칠기 (AFM)

Ra≤0.2nm (5μm*5μm)

구조

마이크로 파이프 밀도

<1 EA/CM2

<10 EA/CM2

<15 EA/CM2

금속 불순물

≤5E10atoms/cm2

NA

BPD

≤1500 EA/CM2

≤3000 EA/CM2

NA

TSD

≤500 EA/CM2

≤1000 EA/CM2

NA

프론트 품질

앞쪽

표면 마감

Si-Face CMP

입자

≤60EA/웨이퍼 (크기 0.3μm)

NA

흠집

≤5EA/mm. 누적 길이 ≤ diameter

누적 길이 ≤2*직경

NA

오렌지 껍질/구덩이/얼룩/줄무늬/균열/오염

없음

NA

에지 칩/인테이션/골절/육각 플레이트

없음

폴리 타입 영역

없음

누적 면적 ≤20%

누적 면적 ≤30%

전면 레이저 표시

없음

뒤로 품질

뒤로 마무리

C-Face CMP

흠집

≤5EA/mm, 누적 길이 ≤2*직경

NA

등 결함 (Edge Chips/Indents)

없음

뒤로 거칠기

Ra≤0.2nm (5μm*5μm)

뒤 레이저 표시

1 mm (상단 가장자리에서)

가장자리

가장자리

모따기

포장

포장

진공 포장으로 에피 레디

멀티 웨이 커 카세트 포장

*참고 :“NA”는 언급되지 않은 요청 항목이 Semi-STD를 참조 할 수 없음을 의미합니다.

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sic wafers

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