3C-SiC Wafer Substrate

Semicera 3C-SiC Wafer Substrates offer superior thermal conductivity and high electrical breakdown voltage, ideal for power electronic and high-frequency devices. These substrates are precision-engineered for optimal performance in harsh environments, ensuring reliability and efficiency. Choose Semicera for innovative and advanced solutions.

Semicera 3C-SiC Wafer Substrates are engineered to provide a robust platform for next-generation power electronics and high-frequency devices. With superior thermal properties and electrical characteristics, these substrates are designed to meet the demanding requirements of modern technology.

The 3C-SiC (Cubic Silicon Carbide) structure of Semicera Wafer Substrates offers unique advantages, including higher thermal conductivity and a lower thermal expansion coefficient compared to other semiconductor materials. This makes them an excellent choice for devices operating under extreme temperatures and high-power conditions.

With a high electrical breakdown voltage and superior chemical stability, Semicera 3C-SiC Wafer Substrates ensure long-lasting performance and reliability. These properties are critical for applications such as high-frequency radar, solid-state lighting, and power inverters, where efficiency and durability are paramount.

Semicera’s commitment to quality is reflected in the meticulous manufacturing process of their 3C-SiC Wafer Substrates, ensuring uniformity and consistency across every batch. This precision contributes to the overall performance and longevity of the electronic devices built upon them.

By choosing Semicera 3C-SiC Wafer Substrates, manufacturers gain access to a cutting-edge material that enables the development of smaller, faster, and more efficient electronic components. Semicera continues to support technological innovation by providing reliable solutions that meet the evolving demands of the semiconductor industry.

Artikel

Produktion

Forschung

Dummy

Kristallparameter

Polytype

4H

Oberflächenorientierungsfehler

4±0.15°

Elektrische Parameter

Dopant

Stickstoff vom Typ N

Widerstand

0,015-0.025OHM · cm

Mechanische Parameter

Durchmesser

150,0 ± 0,2 mm

Dicke

350 ± 25 µm

Primäre flache Orientierung

[1-100]±5°

Primäre flache Länge

47,5 ± 1,5 mm

Sekundäre flache

Keiner

Ttv

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5 mm*5 mm)

≤5 μm (5 mm*5 mm)

≤10 μm (5 mm*5 mm)

Bogen

-15 μm ~ 15 μm

-35 μm ~ 35 μm

-45 μm ~ 45 μm

Kette

≤35 µm

≤45 µm

≤55 µm

Front (Si-Face) Rauheit (AFM)

Ra ≤ 0,2 nm (5 & mgr; m*5 μm)

Struktur

Mikropipe -Dichte

<1 EA/CM2

<10 EA/CM2

<15 EA/CM2

Metallverunreinigungen

≤5E10atoms/cm2

N / A

BPD

≤1500 EA/CM2

≤3000 EA/CM2

N / A

TSD

≤500 EA/CM2

≤1000 EA/CM2

N / A

Frontqualität

Front

Si

Oberflächenbeschaffung

Si-Face CMP

Partikel

≤60ea/Wafer (Größe ≥ 0,3 μm)

N / A

Kratzer

≤5ea/mm. Kumulative Länge ≤ Diameter

Kumulative Länge ≤ 2*Durchmesser

N / A

Orangenschale/Pits/Flecken/Streifen/Risse/Kontamination

Keiner

N / A

Kantenchips/Eingeweide/Fraktur-/Sechskantplatten

Keiner

Polytyperbereiche

Keiner

Kumulative Fläche ≤ 2010TP3T

Kumulative Fläche ≤ 30%

Frontlasermarkierung

Keiner

Rückenqualität

Rückbeschluss

C-Face CMP

Kratzer

≤5ea/mm, kumulative Länge ≤ 2*Durchmesser

N / A

Rückenfehler (Kantenchips/Eingebiete)

Keiner

Rückenrauheit

Ra ≤ 0,2 nm (5 & mgr; m*5 μm)

Rückmarkierung von Laser

1 mm (von der Oberkante)

Rand

Rand

Chamfer

Packaging

Packaging

Epi-ready with vacuum packaging

Multi-wafer cassette packaging

*Notes: “NA” means no request Items not mentioned may refer to SEMI-STD.

tech_1_2_size

SiC wafers

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