Silicon On Insulator Wafer

Semicera’s Silicon On Insulator (SOI) Wafer provides exceptional electrical isolation and thermal management for high-performance applications. Engineered to deliver superior device efficiency and reliability, these wafers are a prime choice for advanced semiconductor technology. Choose Semicera for cutting-edge SOI wafer solutions.

Semicera’s Silicon On Insulator (SOI) Wafer is at the forefront of semiconductor innovation, offering enhanced electrical isolation and superior thermal performance. The SOI structure, consisting of a thin silicon layer on an insulating substrate, provides critical benefits for high-performance electronic devices.

Our SOI wafers are designed to minimize parasitic capacitance and leakage currents, which is essential for developing high-speed and low-power integrated circuits. This advanced technology ensures that devices operate more efficiently, with improved speed and reduced energy consumption, crucial for modern electronics.

The advanced manufacturing processes employed by Semicera guarantee the production of SOI wafers with excellent uniformity and consistency. This quality is vital for applications in telecommunications, automotive, and consumer electronics, where reliable and high-performing components are required.

In addition to their electrical benefits, Semicera’s SOI wafers offer superior thermal insulation, enhancing heat dissipation and stability in high-density and high-power devices. This feature is particularly valuable in applications that involve significant heat generation and require effective thermal management.

By choosing Semicera’s Silicon On Insulator Wafer, you invest in a product that supports the advancement of cutting-edge technologies. Our commitment to quality and innovation ensures that our SOI wafers meet the rigorous demands of today’s semiconductor industry, providing the foundation for next-generation electronic devices.

Elementos

Producción

Investigación

Ficticio

Parámetros de cristal

Politito

4H

Error de orientación de la superficie

4±0.15°

Parámetros eléctricos

Dopante

nitrógeno de tipo N

Resistividad

0.015-0.025ohm · cm

Parámetros mecánicos

Diámetro

150.0 ± 0.2 mm

Espesor

350 ± 25 µm

Orientación plana primaria

[1-100]±5°

Longitud plana primaria

47.5 ± 1.5 mm

Plano secundario

Ninguno

TTV

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5 mm*5 mm)

≤5 μm (5 mm*5 mm)

≤10 μm (5 mm*5 mm)

Arco

-15 μm ~ 15 μm

-35 μm ~ 35 μm

-45 μm ~ 45 μm

Urdimbre

≤35 µm

≤45 µm

≤55 µm

Rugosidad delantera (SI-FACE) (AFM)

RA≤0.2Nm (5 μm*5 μm)

Estructura

Densidad de micropipe

<1 ea/cm2

<10 ea/cm2

<15 ea/cm2

Impurezas de metal

≤5E10atoms/cm2

N / A

BPD

≤1500 ea/cm2

≤3000 ea/cm2

N / A

TSD

≤500 ea/cm2

≤1000 ea/cm2

N / A

Calidad frontal

Frente

Si

Acabado superficial

SI-FACE CMP

Partículas

≤60ea/oblea (tamaño ≥0.3 μm)

N / A

Arañazos

≤5ea/mm. Longitud acumulativa ≤diameter

Longitud acumulativa ≤2*diámetro

N / A

Peel de naranja/pits/manchas/estrías/grietas/contaminación

Ninguno

N / A

Chips de borde/sangría/placas hexagonales

Ninguno

Áreas de politype

Ninguno

Área acumulada ≤20%

Área acumulada ≤30%

Marcado láser delantero

Ninguno

Calidad espalda

Final

CMP C-FACE

Arañazos

≤5EA/mm, longitud acumulativa ≤2*diámetro

N / A

Defectos posteriores (chips/muescas de borde)

Ninguno

Rugosidad

RA≤0.2Nm (5 μm*5 μm)

Marcado láser de espalda

1 mm (desde el borde superior)

Borde

Borde

Chaflán

Embalaje

Embalaje

Lista de EPI con embalaje de vacío

Embalaje de cassette de múltiples obras

*Notas: "NA" significa que ningún elemento de solicitud no mencionado puede referirse a SEMI-STD.

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