Silicon On Insulator Wafer

Semicera’s Silicon On Insulator (SOI) Wafer provides exceptional electrical isolation and thermal management for high-performance applications. Engineered to deliver superior device efficiency and reliability, these wafers are a prime choice for advanced semiconductor technology. Choose Semicera for cutting-edge SOI wafer solutions.

Semicera’s Silicon On Insulator (SOI) Wafer is at the forefront of semiconductor innovation, offering enhanced electrical isolation and superior thermal performance. The SOI structure, consisting of a thin silicon layer on an insulating substrate, provides critical benefits for high-performance electronic devices.

Our SOI wafers are designed to minimize parasitic capacitance and leakage currents, which is essential for developing high-speed and low-power integrated circuits. This advanced technology ensures that devices operate more efficiently, with improved speed and reduced energy consumption, crucial for modern electronics.

The advanced manufacturing processes employed by Semicera guarantee the production of SOI wafers with excellent uniformity and consistency. This quality is vital for applications in telecommunications, automotive, and consumer electronics, where reliable and high-performing components are required.

In addition to their electrical benefits, Semicera’s SOI wafers offer superior thermal insulation, enhancing heat dissipation and stability in high-density and high-power devices. This feature is particularly valuable in applications that involve significant heat generation and require effective thermal management.

By choosing Semicera’s Silicon On Insulator Wafer, you invest in a product that supports the advancement of cutting-edge technologies. Our commitment to quality and innovation ensures that our SOI wafers meet the rigorous demands of today’s semiconductor industry, providing the foundation for next-generation electronic devices.

Elementi

Produzione

Ricerca

Manichino

Parametri cristallini

Politipo

4H

Errore di orientamento della superficie

4±0.15°

Parametri elettrici

Drogante

azoto di tipo n

Resistività

0,015-0,025ohm · cm

Parametri meccanici

Diametro

150,0 ± 0,2 mm

Spessore

350 ± 25 µm

Orientamento piatto primario

[1-100]±5°

Lunghezza piatta primaria

47,5 ± 1,5 mm

Piatto secondario

Nessuno

TTV

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5mm*5mm)

≤5 μm (5 mm*5 mm)

≤10 μm (5 mm*5 mm)

Arco

-15μm ~ 15μm

-35μm ~ 35 μm

-45μm ~ 45μm

Ordito

≤35 µm

≤45 µm

≤55 µm

Front (Si-Face) Rughess (AFM)

RA≤0,2 nm (5μm*5μm)

Struttura

Densità di micrivipe

<1 ea/cm2

<10 ea/cm2

<15 ea/cm2

Impurità dei metalli

≤5E10atoms/cm2

N / A

BPD

≤1500 ea/cm2

≤3000 ea/cm2

N / A

TSD

≤500 ea/cm2

≤1000 ea/cm2

N / A

Qualità anteriore

Davanti

Si

Finitura superficiale

Si-Face CMP

Particelle

≤60ea/wafer (dimensione≥0,3μm)

N / A

Graffi

≤5ea/mm. Lunghezza cumulativa ≤Diameter

Diametro cumulativo della lunghezza ≤2*

N / A

Buccia/pozzi/macchie/striature/crepe/contaminazione

Nessuno

N / A

Bordo chips/riendi/frattura/piastre esadecimale

Nessuno

Aree politepi

Nessuno

Area cumulativa≤20%

Area cumulativa≤30%

Marcatura laser anteriore

Nessuno

Qualità alla schiena

Finitura posteriore

C-FACE CMP

Graffi

≤5ea/mm, lunghezza cumulativa≤2*diametro

N / A

Difetti posteriori (bordo chip/rientri)

Nessuno

Rugosità posteriore

RA≤0,2 nm (5μm*5μm)

Marcatura laser sul retro

1 mm (dal bordo superiore)

Bordo

Bordo

Smussare

Confezione

Confezione

Prepasto EPI con imballaggio a vuoto

Packaging a cassette multi-wafer

*Note : “NA” significa che nessuna richiesta di richiesta non menzionata può fare riferimento a semi-std.

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Sic Wafer

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