Semicera’s Silicon On Insulator (SOI) Wafer provides exceptional electrical isolation and thermal management for high-performance applications. Engineered to deliver superior device efficiency and reliability, these wafers are a prime choice for advanced semiconductor technology. Choose Semicera for cutting-edge SOI wafer solutions.
Semicera’s Silicon On Insulator (SOI) Wafer is at the forefront of semiconductor innovation, offering enhanced electrical isolation and superior thermal performance. The SOI structure, consisting of a thin silicon layer on an insulating substrate, provides critical benefits for high-performance electronic devices.
Our SOI wafers are designed to minimize parasitic capacitance and leakage currents, which is essential for developing high-speed and low-power integrated circuits. This advanced technology ensures that devices operate more efficiently, with improved speed and reduced energy consumption, crucial for modern electronics.
The advanced manufacturing processes employed by Semicera guarantee the production of SOI wafers with excellent uniformity and consistency. This quality is vital for applications in telecommunications, automotive, and consumer electronics, where reliable and high-performing components are required.
In addition to their electrical benefits, Semicera’s SOI wafers offer superior thermal insulation, enhancing heat dissipation and stability in high-density and high-power devices. This feature is particularly valuable in applications that involve significant heat generation and require effective thermal management.
By choosing Semicera’s Silicon On Insulator Wafer, you invest in a product that supports the advancement of cutting-edge technologies. Our commitment to quality and innovation ensures that our SOI wafers meet the rigorous demands of today’s semiconductor industry, providing the foundation for next-generation electronic devices.
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항목 |
생산 |
연구 |
더미 |
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결정 매개 변수 |
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폴리 타입 |
4H |
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표면 방향 오류 |
4±0.15° |
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전기 매개 변수 |
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도펀트 |
N- 타입 질소 |
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저항 |
0.015-0.025ohm · cm |
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기계적 매개 변수 |
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지름 |
150.0 ± 0.2mm |
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두께 |
350 ± 25 µm |
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1 차 평평한 방향 |
[1-100]±5° |
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1 차 평평한 길이 |
47.5 ± 1.5mm |
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보조 아파트 |
없음 |
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TTV |
≤5 µm |
≤10 µm |
≤15 µm |
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LTV |
≤3 μm (5mm*5mm) |
≤5 μm (5mm*5mm) |
≤10 μm (5mm*5mm) |
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절하다 |
-15μm ~ 15μm |
-35μm ~ 35μm |
-45μm ~ 45μm |
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경사 |
≤35 µm |
≤45 µm |
≤55 µm |
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전면 (si-face) 거칠기 (AFM) |
Ra≤0.2nm (5μm*5μm) |
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구조 |
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마이크로 파이프 밀도 |
<1 EA/CM2 |
<10 EA/CM2 |
<15 EA/CM2 |
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금속 불순물 |
≤5E10atoms/cm2 |
NA |
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BPD |
≤1500 EA/CM2 |
≤3000 EA/CM2 |
NA |
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TSD |
≤500 EA/CM2 |
≤1000 EA/CM2 |
NA |
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프론트 품질 |
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앞쪽 |
시 |
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표면 마감 |
Si-Face CMP |
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입자 |
≤60EA/웨이퍼 (크기 0.3μm) |
NA |
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흠집 |
≤5EA/mm. 누적 길이 ≤ diameter |
누적 길이 ≤2*직경 |
NA |
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오렌지 껍질/구덩이/얼룩/줄무늬/균열/오염 |
없음 |
NA |
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에지 칩/인테이션/골절/육각 플레이트 |
없음 |
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폴리 타입 영역 |
없음 |
누적 면적 ≤20% |
누적 면적 ≤30% |
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전면 레이저 표시 |
없음 |
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뒤로 품질 |
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뒤로 마무리 |
C-Face CMP |
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흠집 |
≤5EA/mm, 누적 길이 ≤2*직경 |
NA |
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등 결함 (Edge Chips/Indents) |
없음 |
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뒤로 거칠기 |
Ra≤0.2nm (5μm*5μm) |
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뒤 레이저 표시 |
1 mm (상단 가장자리에서) |
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가장자리 |
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가장자리 |
모따기 |
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포장 |
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포장 |
진공 포장으로 에피 레디 멀티 웨이 커 카세트 포장 |
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*참고 :“NA”는 언급되지 않은 요청 항목이 Semi-STD를 참조 할 수 없음을 의미합니다. |
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