4 Inch High Purity Semi-Insulating HPSI SiC Double-side Polished Wafer Substrate

Semicera’s 4 Inch High Purity Semi-Insulating (HPSI) SiC Double-side Polished Wafer Substrates are precision-engineered for superior electronic performance. These wafers provide excellent thermal conductivity and electrical insulation, ideal for advanced semiconductor applications. Trust Semicera for unparalleled quality and innovation in wafer technology.

Semicera’s 4 Inch High Purity Semi-Insulating (HPSI) SiC Double-side Polished Wafer Substrates are crafted to meet the exacting demands of the semiconductor industry. These substrates are designed with exceptional flatness and purity, offering an optimal platform for cutting-edge electronic devices.

These HPSI SiC wafers are distinguished by their superior thermal conductivity and electrical insulation properties, making them an excellent choice for high-frequency and high-power applications. The double-side polishing process ensures minimal surface roughness, which is crucial for enhancing device performance and longevity.

The high purity of Semicera’s SiC wafers minimizes defects and impurities, leading to higher yield rates and device reliability. These substrates are suitable for a wide range of applications, including microwave devices, power electronics, and LED technologies, where precision and durability are essential.

With a focus on innovation and quality, Semicera utilizes advanced manufacturing techniques to produce wafers that meet the stringent requirements of modern electronics. The double-sided polishing not only improves the mechanical strength but also facilitates better integration with other semiconductor materials.

By choosing Semicera’s 4 Inch High Purity Semi-Insulating HPSI SiC Double-side Polished Wafer Substrates, manufacturers can leverage the benefits of enhanced thermal management and electrical insulation, paving the way for the development of more efficient and powerful electronic devices. Semicera continues to lead the industry with its commitment to quality and technological advancement.

Unid

Produção

Pesquisar

Fictício

Parâmetros de cristal

Polytype

4H

Erro de orientação da superfície

4±0.15°

Parâmetros elétricos

Dopante

nitrogênio do tipo n

Resistividade

0,015-0.025OHM · cm

Parâmetros mecânicos

Diâmetro

150,0 ± 0,2 mm

Grossura

350 ± 25 µm

Orientação plana primária

[1-100]±5°

Comprimento plano primário

47,5 ± 1,5 mm

Apartamento secundário

Nenhum

TTV

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5mm*5mm)

≤5 μm (5mm*5mm)

≤10 μm (5mm*5mm)

Arco

-15μm ~ 15μm

-35μm ~ 35μm

-45μm ~ 45μm

Urdidura

≤35 µm

≤45 µm

≤55 µm

A rugosidade frontal (Si-face) (AFM)

Ra≤0,2 nm (5μm*5μm)

Estrutura

Densidade de micropipe

<1 ea/cm2

<10 ea/cm2

<15 ea/cm2

Impurezas de metal

≤5E10atoms/cm2

N / D

Bpd

≤1500 ea/cm2

≤3000 ea/cm2

N / D

TSD

≤500 ea/cm2

≤1000 ea/cm2

N / D

Qualidade frontal

Frente

Si

Acabamento superficial

Si-face cmp

Partículas

≤60ea/wafer (size≥0,3μm)

N / D

Arranhões

≤5ea/mm. Comprimento cumulativo ≤DIAMETER

Comprimento cumulativo ≤2*diâmetro

N / D

Casca de laranja/poços/manchas/estrias/rachaduras/contaminação

Nenhum

N / D

Chips/recuos/fraturas/placas de fratura/placas hexadecimais

Nenhum

Áreas de poliateiro

Nenhum

Área cumulativa ≤20%

Área cumulativa ≤30%

Marcada a laser dianteira

Nenhum

Qualidade de volta

Final traseiro

CMP C-FACE

Arranhões

≤5ea/mm, comprimento cumulativo≤2*diâmetro

N / D

Defeitos traseiros (chips/recuos de borda)

Nenhum

Rugosidade de volta

Ra≤0,2 nm (5μm*5μm)

Marcação de laser traseiro

1 mm (da borda superior)

Borda

Borda

Chanfro

Embalagem

Embalagem

Epi pronto com embalagem a vácuo

Embalagem de cassetes de várias linhas

*Notas : “NA” significa que nenhum item de solicitação não mencionado pode se referir ao Semi-STD.

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