SOI Wafer Silicon On Insulator

Semicera’s SOI Wafer (Silicon On Insulator) provides exceptional electrical isolation and performance for advanced semiconductor applications. Engineered for superior thermal and electrical efficiency, these wafers are ideal for high-performance integrated circuits. Choose Semicera for quality and reliability in SOI wafer technology.

Semicera’s SOI Wafer (Silicon On Insulator) is designed to deliver superior electrical isolation and thermal performance. This innovative wafer structure, featuring a silicon layer on an insulating layer, ensures enhanced device performance and reduced power consumption, making it ideal for a variety of high-tech applications.

Our SOI wafers offer exceptional benefits for integrated circuits by minimizing parasitic capacitance and improving device speed and efficiency. This is crucial for modern electronics, where high performance and energy efficiency are essential for both consumer and industrial applications.

Semicera employs advanced manufacturing techniques to produce SOI wafers with consistent quality and reliability. These wafers provide excellent thermal insulation, making them suitable for use in environments where heat dissipation is a concern, such as in high-density electronic devices and power management systems.

The use of SOI wafers in semiconductor fabrication allows for the development of smaller, faster, and more reliable chips. Semicera’s commitment to precision engineering ensures that our SOI wafers meet the high standards required for cutting-edge technologies in fields like telecommunications, automotive, and consumer electronics.

Choosing Semicera’s SOI Wafer means investing in a product that supports the advancement of electronic and microelectronic technologies. Our wafers are designed to provide enhanced performance and durability, contributing to the success of your high-tech projects and ensuring that you stay at the forefront of innovation.

Unid

Produção

Pesquisar

Fictício

Parâmetros de cristal

Polytype

4H

Erro de orientação da superfície

4±0.15°

Parâmetros elétricos

Dopante

nitrogênio do tipo n

Resistividade

0,015-0.025OHM · cm

Parâmetros mecânicos

Diâmetro

150,0 ± 0,2 mm

Grossura

350 ± 25 µm

Orientação plana primária

[1-100]±5°

Comprimento plano primário

47,5 ± 1,5 mm

Apartamento secundário

Nenhum

TTV

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5mm*5mm)

≤5 μm (5mm*5mm)

≤10 μm (5mm*5mm)

Arco

-15μm ~ 15μm

-35μm ~ 35μm

-45μm ~ 45μm

Urdidura

≤35 µm

≤45 µm

≤55 µm

A rugosidade frontal (Si-face) (AFM)

Ra≤0,2 nm (5μm*5μm)

Estrutura

Densidade de micropipe

<1 ea/cm2

<10 ea/cm2

<15 ea/cm2

Impurezas de metal

≤5E10atoms/cm2

N / D

Bpd

≤1500 ea/cm2

≤3000 ea/cm2

N / D

TSD

≤500 ea/cm2

≤1000 ea/cm2

N / D

Qualidade frontal

Frente

Si

Acabamento superficial

Si-face cmp

Partículas

≤60ea/wafer (size≥0,3μm)

N / D

Arranhões

≤5ea/mm. Comprimento cumulativo ≤DIAMETER

Comprimento cumulativo ≤2*diâmetro

N / D

Casca de laranja/poços/manchas/estrias/rachaduras/contaminação

Nenhum

N / D

Chips/recuos/fraturas/placas de fratura/placas hexadecimais

Nenhum

Áreas de poliateiro

Nenhum

Área cumulativa ≤20%

Área cumulativa ≤30%

Marcada a laser dianteira

Nenhum

Qualidade de volta

Final traseiro

CMP C-FACE

Arranhões

≤5ea/mm, comprimento cumulativo≤2*diâmetro

N / D

Defeitos traseiros (chips/recuos de borda)

Nenhum

Rugosidade de volta

Ra≤0,2 nm (5μm*5μm)

Marcação de laser traseiro

1 mm (da borda superior)

Borda

Borda

Chanfro

Embalagem

Embalagem

Epi pronto com embalagem a vácuo

Embalagem de cassetes de várias linhas

*Notas : “NA” significa que nenhum item de solicitação não mencionado pode se referir ao Semi-STD.

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