Silicon On Insulator Wafer

Semicera’s Silicon On Insulator (SOI) Wafer provides exceptional electrical isolation and thermal management for high-performance applications. Engineered to deliver superior device efficiency and reliability, these wafers are a prime choice for advanced semiconductor technology. Choose Semicera for cutting-edge SOI wafer solutions.

Semicera’s Silicon On Insulator (SOI) Wafer is at the forefront of semiconductor innovation, offering enhanced electrical isolation and superior thermal performance. The SOI structure, consisting of a thin silicon layer on an insulating substrate, provides critical benefits for high-performance electronic devices.

Our SOI wafers are designed to minimize parasitic capacitance and leakage currents, which is essential for developing high-speed and low-power integrated circuits. This advanced technology ensures that devices operate more efficiently, with improved speed and reduced energy consumption, crucial for modern electronics.

The advanced manufacturing processes employed by Semicera guarantee the production of SOI wafers with excellent uniformity and consistency. This quality is vital for applications in telecommunications, automotive, and consumer electronics, where reliable and high-performing components are required.

In addition to their electrical benefits, Semicera’s SOI wafers offer superior thermal insulation, enhancing heat dissipation and stability in high-density and high-power devices. This feature is particularly valuable in applications that involve significant heat generation and require effective thermal management.

By choosing Semicera’s Silicon On Insulator Wafer, you invest in a product that supports the advancement of cutting-edge technologies. Our commitment to quality and innovation ensures that our SOI wafers meet the rigorous demands of today’s semiconductor industry, providing the foundation for next-generation electronic devices.

Artikel

Produktion

Forschung

Dummy

Kristallparameter

Polytype

4H

Oberflächenorientierungsfehler

4±0.15°

Elektrische Parameter

Dopant

Stickstoff vom Typ N

Widerstand

0,015-0.025OHM · cm

Mechanische Parameter

Durchmesser

150,0 ± 0,2 mm

Dicke

350 ± 25 µm

Primäre flache Orientierung

[1-100]±5°

Primäre flache Länge

47,5 ± 1,5 mm

Sekundäre flache

Keiner

Ttv

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5 mm*5 mm)

≤5 μm (5 mm*5 mm)

≤10 μm (5 mm*5 mm)

Bogen

-15 μm ~ 15 μm

-35 μm ~ 35 μm

-45 μm ~ 45 μm

Kette

≤35 µm

≤45 µm

≤55 µm

Front (Si-Face) Rauheit (AFM)

Ra ≤ 0,2 nm (5 & mgr; m*5 μm)

Struktur

Mikropipe -Dichte

<1 EA/CM2

<10 EA/CM2

<15 EA/CM2

Metallverunreinigungen

≤5E10atoms/cm2

N / A

BPD

≤1500 EA/CM2

≤3000 EA/CM2

N / A

TSD

≤500 EA/CM2

≤1000 EA/CM2

N / A

Frontqualität

Front

Si

Oberflächenbeschaffung

Si-Face CMP

Partikel

≤60ea/Wafer (Größe ≥ 0,3 μm)

N / A

Kratzer

≤5ea/mm. Kumulative Länge ≤ Diameter

Kumulative Länge ≤ 2*Durchmesser

N / A

Orangenschale/Pits/Flecken/Streifen/Risse/Kontamination

Keiner

N / A

Kantenchips/Eingeweide/Fraktur-/Sechskantplatten

Keiner

Polytyperbereiche

Keiner

Kumulative Fläche ≤ 2010TP3T

Kumulative Fläche ≤ 30%

Frontlasermarkierung

Keiner

Rückenqualität

Rückbeschluss

C-Face CMP

Kratzer

≤5ea/mm, kumulative Länge ≤ 2*Durchmesser

N / A

Rückenfehler (Kantenchips/Eingebiete)

Keiner

Rückenrauheit

Ra ≤ 0,2 nm (5 & mgr; m*5 μm)

Rückmarkierung von Laser

1 mm (von der Oberkante)

Rand

Rand

Chamfer

Packaging

Packaging

Epi-ready with vacuum packaging

Multi-wafer cassette packaging

*Notes: “NA” means no request Items not mentioned may refer to SEMI-STD.

tech_1_2_size

SiC wafers

Newletter

Ich freue mich auf Ihren Kontakt mit uns