Silicon On Insulator Wafer

Semicera’s Silicon On Insulator (SOI) Wafer provides exceptional electrical isolation and thermal management for high-performance applications. Engineered to deliver superior device efficiency and reliability, these wafers are a prime choice for advanced semiconductor technology. Choose Semicera for cutting-edge SOI wafer solutions.

Semicera’s Silicon On Insulator (SOI) Wafer is at the forefront of semiconductor innovation, offering enhanced electrical isolation and superior thermal performance. The SOI structure, consisting of a thin silicon layer on an insulating substrate, provides critical benefits for high-performance electronic devices.

Our SOI wafers are designed to minimize parasitic capacitance and leakage currents, which is essential for developing high-speed and low-power integrated circuits. This advanced technology ensures that devices operate more efficiently, with improved speed and reduced energy consumption, crucial for modern electronics.

The advanced manufacturing processes employed by Semicera guarantee the production of SOI wafers with excellent uniformity and consistency. This quality is vital for applications in telecommunications, automotive, and consumer electronics, where reliable and high-performing components are required.

In addition to their electrical benefits, Semicera’s SOI wafers offer superior thermal insulation, enhancing heat dissipation and stability in high-density and high-power devices. This feature is particularly valuable in applications that involve significant heat generation and require effective thermal management.

By choosing Semicera’s Silicon On Insulator Wafer, you invest in a product that supports the advancement of cutting-edge technologies. Our commitment to quality and innovation ensures that our SOI wafers meet the rigorous demands of today’s semiconductor industry, providing the foundation for next-generation electronic devices.

Unid

Produção

Pesquisar

Fictício

Parâmetros de cristal

Polytype

4H

Erro de orientação da superfície

4±0.15°

Parâmetros elétricos

Dopante

nitrogênio do tipo n

Resistividade

0,015-0.025OHM · cm

Parâmetros mecânicos

Diâmetro

150,0 ± 0,2 mm

Grossura

350 ± 25 µm

Orientação plana primária

[1-100]±5°

Comprimento plano primário

47,5 ± 1,5 mm

Apartamento secundário

Nenhum

TTV

≤5 µm

≤10 µm

≤15 µm

LTV

≤3 μm (5mm*5mm)

≤5 μm (5mm*5mm)

≤10 μm (5mm*5mm)

Arco

-15μm ~ 15μm

-35μm ~ 35μm

-45μm ~ 45μm

Urdidura

≤35 µm

≤45 µm

≤55 µm

A rugosidade frontal (Si-face) (AFM)

Ra≤0,2 nm (5μm*5μm)

Estrutura

Densidade de micropipe

<1 ea/cm2

<10 ea/cm2

<15 ea/cm2

Impurezas de metal

≤5E10atoms/cm2

N / D

Bpd

≤1500 ea/cm2

≤3000 ea/cm2

N / D

TSD

≤500 ea/cm2

≤1000 ea/cm2

N / D

Qualidade frontal

Frente

Si

Acabamento superficial

Si-face cmp

Partículas

≤60ea/wafer (size≥0,3μm)

N / D

Arranhões

≤5ea/mm. Comprimento cumulativo ≤DIAMETER

Comprimento cumulativo ≤2*diâmetro

N / D

Casca de laranja/poços/manchas/estrias/rachaduras/contaminação

Nenhum

N / D

Chips/recuos/fraturas/placas de fratura/placas hexadecimais

Nenhum

Áreas de poliateiro

Nenhum

Área cumulativa ≤20%

Área cumulativa ≤30%

Marcada a laser dianteira

Nenhum

Qualidade de volta

Final traseiro

CMP C-FACE

Arranhões

≤5ea/mm, comprimento cumulativo≤2*diâmetro

N / D

Defeitos traseiros (chips/recuos de borda)

Nenhum

Rugosidade de volta

Ra≤0,2 nm (5μm*5μm)

Marcação de laser traseiro

1 mm (da borda superior)

Borda

Borda

Chanfro

Embalagem

Embalagem

Epi pronto com embalagem a vácuo

Embalagem de cassetes de várias linhas

*Notas : “NA” significa que nenhum item de solicitação não mencionado pode se referir ao Semi-STD.

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